In semiconductor fabrication processes, the resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication equipment purchased for larger technology nodes, double exposure methods have been developed.
Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession. As a result, a minimum line spacing in the combined pattern can be reduced while maintaining good resolution. One form of double exposure is referred to as double patterning technology (DPT). DPT is a layout splitting method analogous to a two coloring problem for layout splitting in graph theory. The layout polygon and critical space are similar to the vertex and edge of the graph respectively. Two adjacent vertices connected with an edge should be assigned different colors. In double patterning, two “color types” are assigned. Each pattern on the layer is assigned a first or second “color”; the patterns of the first color are formed by a first mask, and the patterns of the second color are formed by a second mask. A graph is typically considered 2-colorable only if it contains no odd-cycle and loop. Although DPT has advantages, it is computationally intensive.
A final Integrated Circuit (IC) layout may be made from a plurality of smaller cell layouts. These cells may be retrieved from a cell library and may be DPT compliant with patterns distributed between multiple masks. When multiple cells are combined, it is possible to join the cells in a way that does not yield a double patterning decomposable layout.